During the formation of integrated circuits (IC's) on the surface of a semiconductor substrate or wafer, the individual circuits or groups of circuits must be tested to determine that they were fabricated correctly and are functioning properly. Such testing is usually done upon completion of the wafer processing to determine if the wafer is suitable for being packaged into individual IC chips. Alternatively, the IC's might be tested at various stages during their processing to determine if future processing is desirable for a particular wafer or set of wafers, or whether the wafer or wafers should be discarded.
The testing of IC's on a wafer is done by using a probing machine or prober. The prober has a number of finely-constructed, elongated electrical probes which contact the surface of the wafer to make electrical contact with individual IC's thereon. The probes are connected to diagnostic equipment which is used to verify the operational characteristics of an IC, such as its resistance characteristics and its signal handling capabilities, for example.
Integrated circuit probers are commercially available, and one such suitable prober is available from KLA Instruments Corporation of San Jose, Calif. under Model No. KLA-1007. Probers usually have multiple, elongated test probes mounted next to each other on a planar probe card. The elongated probes extend downwardly from the probe card at various positions on the card. The probe card is a printed circuit board having conductive paths that are connected to the individual probes for electrically coupling the probes to the diagnostic equipment. The probe card, in turn, is mounted to a planar probe card mount or load board that is made of a suitable polymer such as glass epoxy laminate. The planar probe card and card mount form a probe card assembly. The individual elongated test probes, which may be, for example, tungsten or a beryllium/copper alloy, are connected through the probe card assembly to test leads on the probe card mount. The test leads provide a low resistance or "zero resistance" path to the probes for electrically connecting them to the diagnostic equipment.
In a prober, the planar probe card assembly is positioned opposite to (usually above) and parallel to the planar surface of the semiconductor wafer to be probed and tested. The wafer is supported below the assembly and probes by a suitable wafer chuck of the prober. For probing purposes, the chuck moves or translates vertically toward and away from the probe card assembly to position the wafer and IC's thereon against the ends of the test probes.
Ideally, the planar probe card assembly is parallel to the wafer surface and chuck and the probe ends all lie in a single plane which is also parallel to the plane of the wafer surface to be tested. In that way, when the chuck is moved toward the probe card assembly, the test probe ends contact the wafer surface evenly and at the same time and in the proper positions around the wafer. Usually the wafer chuck is moved slightly past the chuck position of initial probe contact with the wafer to ensure a good electrical contact between the probes and the ICs being tested. However, when the test probes are unevenly positioned and are not planar in a plane which is parallel with the plane of the wafer surface, damage to both the probes and the wafer may occur, because the ends of the test probes do not contact the wafer surface evenly as desired.
It will be understood by a person of ordinary skill in the art, that uneven probe positioning and uneven probe end contact on the wafer surface may be caused by a number of factors. For example, tilting of the planar probe card assembly and probes, or tilting of the wafer surface, each with respect to the other parallel component, will cause uneven probe end contact. Uneven contact is also caused by probe ends which are not properly positioned on the probe card assembly and are non-planar and/or non-parallel with respect to the plane of the wafer surface. More specifically, uneven contact exists when the probe ends are properly positioned on the probe card assembly, but the probe card assembly plane is not parallel to the wafer surface plane. Conversely, uneven contact also exists when the probe card assembly plane is parallel to the wafer surface plane, but the individual probe ends are not planar, and in a plane parallel with respect to the wafer surface plane. Both conditions will be referred to herein as non-planar probes, wherein planarity of the probes is desired. Planar probes will have ends all within a single plane, and that plane will be generally parallel to the wafer surface plane.
If the probes are non-planar with respect to the plane of the wafer surface, one or more of the probes will contact the wafer surface before the other probes. Uneven surface contact causes uneven wear of the probes at their ends and early replacement of certain probes on the board is then required. Probe replacement is an expensive and time-consuming endeavor. If the wafer chuck is moved only until certain of the probes first make contact, then other of the probes, which are not in the plane of the contacting probe, will not make solid electrical contact with the wafer. This prevents accurate testing of the wafer ICs.
Damage to the wafer is also caused by uneven probe contact. The uneven contact of the probes causes certain of the probes to contact the wafer before the other probes, as mentioned above. To compensate for the skewed or uneven probe contact, the chuck is moved further in the direction of the probe card assembly. While a certain amount of "over travel" of the chuck is used to ensure proper probe contact, too much over travel causes the ends of the probes which contacted earliest to slide out of their proper position on the wafer surface. The probe ends thus scratch the surface of the wafer as they slide, causing damage to the ICs formed at the surface. Even if no physical damage occurs, movement of the probe end from the desired position prevents accurate testing of the ICs.
Still further, uneven contact of the probes creates uneven stress on the probes. The probes are formed to be resilient under certain stresses; however, overstressing will cause the probes to break. The breakage will not only require replacement of the particular probe, but may damage the wafer as well.
Various prior art methods have been used for achieving parallel orientation and planarity between the individual probe ends and the wafer surface. However, those methods have proven generally unsatisfactory. Once such method is to imprecisely visually estimate the planarity and parallel orientation of the probe ends by variations in the size of the marks left on the wafer surface. Such a task is imprecise and tedious. Furthermore, the difficulty of estimating the planarity in such a way is further exacerbated by the small scale of the ICs. Slight variations of the probe ends from the desired plane and parallel orientation may be sufficient to cause damage to the IC before it is detectable in such fashion.
Another method is to make planarity measurements of the probe card mount in the wafer prober without the probe card attached thereto. Such planarity measurements are very time-consuming and will not guarantee that planarity and parallel orientation of the probes will be maintained upon mounting the probe card.
Furthermore, even when non-planarity of the probes is detected, it is still difficult to determine how the probes or probe card assembly should be adjusted for proper probe contact.
Therefore, it is an objective of the present invention to ensure planarity and parallel orientation of wafer test probes with respect to the surface of a wafer.
It is another objective of the present invention to provide even contact between the ends of the test probes and the wafer surface during testing procedures.
It is still another objective of the invention to provide an indication of the planarity or non-planarity of test probes with respect to a wafer surface.
It is another objective of the invention to prevent probe damage to the integrated circuits of a wafer being tested.
It is still another objective of the invention to verify the planarity and parallel orientation of the test probe ends in a simple and efficient manner.